In a system in which a bus such as a system bus is shared by multiple devices (IP cores), a controller (bus arbiter) allocates access to the bus among the IP cores. Each IP core requests access to the bus through the controller. Whenever the controller receives a request from an IP core, the controller arbitrates among the IP cores to allocate access to the bus to the IP core according to a preset rule such as priority given to each IP core.
FIG. 7 schematically illustrates a configuration of a bus control system of this type. As illustrated in FIG. 7, the controller (bus arbiter) 701 and multiple IP cores 702 are connected onto a bus 703. The IP cores 702 share the bus 703 under the control of the controller 701.
An existing technique of this type has been disclosed in Patent document 1 (Published Unexamined Japanese Patent Application No. 6-332850) in which, in a computer system where multiple devices and a bus controller which arbitrates bus ownership of a system bus are connected to the system bus, the bus controller has the function of allocating a certain amount of data transfer time to channels to which the devices are connected at certain time intervals. With this configuration, the system allows multimedia data including audio and moving image data to be handled in a manner similar to that in data transfer by conventional I/O devices.
The above system where multiple IP cores share the bus as described above was unable to explicitly ensure hard real-time accessibility and bus-band availability. These can be ensured only by adjusting the bus occupancy rates among the IP cores. Another problem with the system is that when a particular IP core has a long burst length or a high priority bus access, other IP cores have a much less chance of gaining bus access.